1. Field of the Invention
The present invention relates to a network port for receiving, storing, and then forwarding cells derived from network data transmissions, and in particular to a system for adjusting rates at which the port forwards the cells in response to back pressure.
2. Description of Related Art
A typical network switch for routing data transmissions (packets) between network buses includes a set of input ports, a set of output ports, and a switch fabric providing data signal paths between the input and output ports. Each input port includes a memory for storing each incoming packet until the input port can forward it via the switch to an output port. Each output port also includes a memory for each packet arriving via the switch fabric until it can forward the packet outward on a network bus.
Although packets may be of variable size, a switch port may organize its memory into a set of memory blocks of uniform size, each sufficiently large to hold the largest possible packet. However when most packets are much smaller than the maximum allowable size, much of the storage capacity of most memory blocks is wasted. To make more efficient use of memory space, an input port may convert each incoming packet into a sequence of relatively small cells of uniform size. A traffic manager within the input port stores each cell derived from a packet in a separate memory block sized just large enough to hold one cell. Although breaking each packet into a sequence of uniform sized cells increases the port's packet processing overhead, since the port has to keep track where cells of each packet are stored, the port makes more efficient use of the data storage capacity of the port's cell memory because most memory blocks are completely filled with packet data.
Some time after storing the cells derived from an incoming packet in a cell memory, a typical input port's traffic manager reads the cells out of the cell memory in appropriate order and places them in a “first-in, first-out” (FIFO) buffer. When the FIFO buffer is not empty, a switch interface circuit requests a path through the switch fabric to an output port that is to receive the longest-stored (“head of line”) cell in the FIFO buffer, forwards the cell to the output port when the path is available and then shifts the cell out of the FIFO buffer. The output port's traffic manager stores the cell in the output port's cell memory and thereafter reads the cell out of that cell memory and forwards it to another FIFO buffer. The output port's protocol processor reassembles cells stored in that FIFO buffer into packets, and forwards the packets outward on a network bus.
Some network systems assign each packet to one of several “flows”; all packets assigned to the same flow arrive at the same switch input port and depart from the same switch output port. Each flow has an associated “class of service” which may A specify an average minimum and/or maximum rate at which cells assigned to the flow must be forwarded, or which may specify an average fixed rate at which cell of the flow must be forwarded. Even though a port may at times have the bandwidth available to forward cells of various flows at higher rates, the port's traffic manager tries to control the rate at which it forwards cells from the port's cell memory of each flow so that it remains within the range specified by that flow's class of service.
An input or output port's FIFO buffers are needed to temporarily store cells read out of the cell memory until they can be forwarded since a times a port may be unable to forward cells as fast as the traffic manager sends them out of the cell memory. For example, in an input port this can happen when an output port to which cells are destined is busy receiving cells from other ports. The FIFO buffer typically sends a “back pressure” signal to the traffic manager when its internal cell buffer is filled to tell the traffic manager to stop sending cells. In some systems, the back pressure signal conveys a code indicating how much of the capacity of FIFO buffer is currently unused. For example when such a back pressure signal indicates the FIFO buffer fill has reached a threshold level below the maximum capacity, the traffic manager may stop sending cells of lower priority flows out of the cell memory to the FIFO buffer while continuing to send cells of higher priority cells to the FIFO buffer until it is full.
When a switch interface circuit queues all incoming cells in a FIFO buffer, a head-of-line cell in the FIFO buffer destined for an output port that is busy will prevent the port from forwarding cells to output ports that are not busy. To prevent such “head-of-line” blocking, a port may holding cells read out of the cell memory that destined for separate output port in separate FIFO buffers so one busy output port will not block flow of cells to other output ports. In such case each FIFO buffer can send a separate back pressure signal back to the traffic manager and the traffic manager need only halt forwarding of only those flows destined to output ports that are blocked.
While a traffic manger tries to maintain an average forwarding rate for cells of each flow, a halt forwarding of cells of a flow due to back pressure that is long enough to cause a FIFO buffer to fill up, will require the traffic manager to shut off the flow of cells of one or more flows passing from the cell memory to the FIFO buffer. Such a halt in forwarding of cells to the FIFO buffer will adversely impact the average cell rate of one or more flows. The amount of time that a FIFO buffer can be blocked without requiring the traffic manager to reduce the rate at which it forwards cells into the FIFO buffer increases with the capacity of the FIFO buffer. Hence by increasing the size of the FIFO buffer we improve the system's ability to maintain average cell forwarding rates despite prolonged forwarding halts due to back pressure.
But FIFO buffers capable of holding large numbers of cells are expensive. What is needed is a system that permits the traffic manager to maintain desired average cell forwarding rates for each flow despite relatively long halts in cell forwarding from the switch interface circuit due to back pressure without having to employ large FIFO buffers.